Line fill techniques are known. Typically, in a data processing apparatus, a cache is provided to store data for subsequent use by a processor core. When data is first requested by the processor core it is read from main memory and provided to the processor core and stored in the cache.
In many data processing apparatuses, it is assumed that if a processor core requires a particular data value then it is likely that the processor core will need other data values located in addresses adjacent to that data value. Accordingly, it is typical for not only the requested data value to be returned from the main memory but also for other data values to provide a complete cache line to be returned from main memory and stored in the cache. Hence, a line fill buffer may typically be provided into which the complete cache line may be stored prior to being allocated to the cache.
Accordingly, should the processor core indeed require another data value from within that cache line then this data value will already be allocated within the cache and can be accessed by the core without having to perform a time consuming data access to the main memory.
In many data processing apparatus a single line fill buffer is sufficient to store data for line fill requests. However, since each line fill request may take a relatively large number of cycles to complete then there is a finite time before which another line fill request can be initiated. Hence, it is also known to provide additional line fill buffers in order to enable multiple line fill requests to occur simultaneously.
It is desired to provide an improved line fill technique.